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1 MSPS 16-/14-Bit Analog I/O Port AD15700
FEATURES 16-Bit A/D Converter 1 MSPS S/(N + D): 90 dB Typ @ 250 kHz No Pipeline Delay 14-Bit D/A Converter Settling Time: 1 s S/N: 92 dB Typ 2 80 MHz Amplifiers 30 V/ s Slew Rate Rail-to-Rail Input and Output Output Current 15 mA 2 Gain Setting Center Tapped Resistors Resistor Ratio Tracking: 2 ppm/ C Unipolar Operation SPI(R)/QSPITM/MICROWIRETM/DSP Compatible 132 mW Typical Power Dissipation APPLICATIONS Optical MEMS Mirror Control Industrial Process Control Data Acquisition Instrumentation Communication FUNCTIONAL BLOCK DIAGRAM
VDD_DAC DGND_DAC
VREF
14-BIT DAC
VOUT_DAC AGND_DAC
CS_DAC DIN SCLK CONTROL LOGIC
14-BIT DATA LATCH
-IN1 +IN1 +VS1
SERIAL INPUT REGISTER
VOUT1 -VS1
COMMON
AD15700
1.5k 1.5k
RA1 RB1
REF REFGND IND(4R) INC(4R) INB(2R) INA(R) INGND VOUT2 +VS2 +IN2 -IN2 -VS2 CLOCK SAR ADC CONTROL LOGIC AND CALIBRATION CIRCUITRY 4R 4R 2R R SWITCHED CAP DAC PARALLEL INTERFACE 16 SERIAL PORT
RC1 RPAD1 OVDD OGND
SER/PAR BUSY D[15:0] CS_ADC RD OB/2C BYTESWAP AVDD
GENERAL DESCRIPTION
PD RESET 1.5k RPAD2 1.5k AGND_ADC
The AD15700 is a precision component to interface analog input and output channels to a digital processor. It is ideal for arealimited applications that require maximum circuit density. The AD15700 contains the functionality of a 16-bit, 1 MSPS charge redistribution SAR analog-to-digital converter that operates from a 5 V power supply. The high speed 16-bit sampling ADC incorporates a resistor input scaler that allows various input ranges, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. The AD15700 also contains a 14-bit, serial input, voltage output DAC that operates from a 5 V supply and has a settling time of 1 ms. Two single- or split-supply voltage feedback amplifiers with rail-to-rail input and output characteristics featuring 80 MHz of small signal bandwidth and 10 mV/C offset drift provide ADC and DAC buffering capability. The center tapped 3 kW resistors are precision resistor networks with 2 ppm/C ratio tracking that provide low gain drift when used for scaling. The ADC, DAC, and amp functions are electrically isolated from each other to provide maximum design flexibility. Input and output signal conditioning circuits for the converters can be easily configured with short interconnects under the device at the board level. The AD15700 is available in a 10 mm CSPBGA package. REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
RA2 RB2 RC2
WARP CNVST IMPULSE
DVDD
DGND ADC
PRODUCT HIGHLIGHTS
1. Fast Throughput ADC. The AD15700 incorporates a high speed, 1 MSPS, 16-bit SAR ADC. 2. Superior ADC INL. The 16-bit ADC has a maximum integral nonlineariy of 2.5 LSB with no missing codes. 3. Two Precision Resistor Networks with 2 ppm/C Ratio Tracking for Gain Setting. 4. Low Power Consumption. Typically 132 mW at maximum performance levels. 5. Industrial Temperature Range: -40C to +85C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD15700-SPECIFICATIONS
16-BIT ADC ELECTRICAL CHARACTERISTICS
Parameter RESOLUTION ANALOG INPUT Voltage Range Common-Mode Input Voltage Analog Input CMRR Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate Time between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Transition Noise Bipolar Zero Error 2, TMIN to TMAX VIND - VINGND VINGND fIN = 100 kHz Condition
(-40 C to +85 C, AVDD = DVDD = 5 V, 0VDD = 2.7 V to 5.25 V, unless otherwise noted.)
Min 16 4 REF, 0 V to 4 REF, 2 REF (See Table I) -0.1 +0.5 74 See Table I 1 1000 1 1.25 800 1.5 666 +2.5 0.7 -45 0.1% +45 Typ Max Unit Bits
V dB
In Warp Mode In Warp Mode In Warp Mode In Normal Mode In Normal Mode In Impulse Mode In Impulse Mode
1
0 0 -2.5 16
ms kSPS ms ms kSPS ms kSPS LSB1 Bits LSB LSB % of FSR % of FSR % of FSR % of FSR LSB dB3 dB dB dB dB dB dB MHz ns ps rms ns V mA
5 V Range, Normal or Impulse Modes Other Range or Mode
Bipolar Full-Scale Error 2, TMIN to TMAX Unipolar Zero Error 2, TMIN to TMAX Unipolar Full-Scale Error 2, TMIN to TMAX Power Supply Sensitivity AVDD = 5 V 5% AC ACCURACY Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) -3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response REFERENCE External Reference Voltage Range External Reference Current Drain DIGITAL INPUTS Logic Levels VIL VIH IIL IIH fIN = 20 kHz fIN = 250 kHz fIN = 250 kHz fIN = 20 kHz fIN = 250 kHz fIN = 20 kHz fIN = 250 kHz, -60 dB Input
-0.38 -0.18 -0.76
9.5 90 90 100 -100 -100 90 30 9.6 2 5
+0.38 +0.18 +0.76
89
-96
88.5
Full-Scale Step 2.3 1 MSPS Throughput 2.5 200
250 3.0
-0.3 +2.0 -1 -1
+0.8 DVDD + 0.3 +1 +1
V V mA mA
-2-
REV. A
AD15700
Parameter DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current4 AVDD DVDD5 OVDD5 Power Dissipation5, 6 In Power-Down Mode8 TEMPERATURE RANGE Specified Performance TMIN to TMAX -40 ISINK = 1.6 mA ISOURCE = -570 mA Condition Min Typ Max Unit Parallel or Serial 16-Bit Conversion Results Available Immediately after Completed Conversion 0.4 OVDD - 0.6
V V
4.75 4.75 2.7
5 5
5.25 5.25 5.25
V V V mA mA mA mW mW mW mW C
666 kSPS Throughput7 100 SPS Throughput7 1 MSPS Throughput4
15 7.2 37 84 15 112
95 125 1 +85
NOTES 1 LSB means Least Significant Bit. With the 5 V input range, one LSB is 152.588 mV. 2 These specifications do not include the error contribution from the external reference. 3 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4 In Warp Mode. 5 Tested in Parallel Reading Mode. 6 Tested with the 0 V to 5 V range and VIN - VINGND = 0 V. 7 In Impulse Mode. 8 With OVDD below DVDD + 0.3 V and all digital inputs forced to OVDD or OGND, respectively. Specifications subject to change without notice.
Table I. Analog Input Configuration
Input Voltage Range 4 REF 2 REF REF 0 V to 4 REF 0 V to 2 REF 0 V to REF
IND(4R) VIN VIN VIN VIN VIN VIN
INC(4R) INGND VIN VIN VIN VIN VIN
INB(2R) INGND INGND VIN INGND VIN VIN
INA(R) REF REF REF INGND INGND VIN
Input Impedance1 1.63 kW 948 W 711 W 948 W 711 W Note 2
NOTES 1 Typical analog input impedance. 2 For this range, the input is high impedance.
REV. A
-3-
AD15700 16-BIT ADC TIMING CHARACTERISTICS (-40 C to +85 C, AVDD = DVDD = 5 V, 0VDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter Refer to Figures 14 and 15 Convert Pulsewidth Time between Conversions (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except in Master Serial Read after Convert Mode (Warp Mode/Normal Mode/Impulse Mode) Aperture Delay End of Conversion to BUSY LOW Delay Conversion Time (Warp Mode/Normal Mode/Impulse Mode) Acquisition Time RESET Pulsewidth Refer to Figures 16, 17, and 18 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY LOW Delay Bus Access Request to DATA Valid Bus Relinquish Time Refer to Figures 20 and 21 (Master Serial Interface Modes) CS_ADC LOW to SYNC Valid Delay CS_ADC LOW to Internal SCLK Valid Delay CS_ADC LOW to SDOUT Delay CNVST LOW to SYNC Delay (Read During Convert) (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay 3 Internal SCLK Period3 Internal SCLK HIGH3 Internal SCLK LOW3 SDOUT Valid Setup Time3 SDOUT Valid Hold Time3 SCLK Last Edge to SYNC Delay3 CS_ADC HIGH to SYNC HI-Z CS_ADC HIGH to Internal SCLK HI-Z CS_ADC HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read after Convert3 CNVST LOW to SYNC Asserted Delay Master Serial Read after Convert SYNC Deasserted to BUSY LOW Delay Refer to Figures 22 and 24 (Slave Serial Interface Modes) External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK HIGH External SCLK LOW
2
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37
Min 5 1/1.25/1.5
Typ
Max
Unit ns ms ns ms ns ns ms ms ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns
Note 1 30 0.75/1/1.25 2
10 0.75/1/1.25 1 10 0.75/1/1.25 20 5 40 15 10 10 10 25/275/525 4 25 15 9 4.5 2 3
40
10 10 10 See Table II 0.75/1/1.25 25 5 3 5 5 25 10 10
16
NOTES 1 In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 2 In Serial Interface Modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum. 3 In serial master Read during Convert Mode. See Table II. Specifications subject to change without notice.
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REV. A
AD15700
Table II. Serial Clock Timings in Master Read after Convert
DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum BUSY HIGH Width Maximum (Warp) BUSY HIGH Width Maximum (Normal) BUSY HIGH Width Maximum (Impulse)
Symbol
0 0 4 25 40 15 9 4.5 2 3 1.5 1.75 2
0 1 20 50 70 25 24 22 4 60 2 2.25 2.5
1 0 20 100 140 50 49 22 30 140 3 3.25 3.5
1 1 20 200 280 100 99 22 89 300 5.25 5.5 5.75
Unit ns ns ns ns ns ns ns ns ms ms ms
t18 t19 t19 t20 t21 t22 t23 t24 t28 t28 t28
1.6mA
IOL
TO OUTPUT PIN
1.4V CL 60pF 500mA IOH
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs, CL = 10 pF
0.8V
2V
tDELAY
2V 0.8V
tDELAY
2V 0.8V
Figure 2. Voltage Reference Levels for Timing
REV. A
-5-
AD15700 14-BIT DAC ELECTRICAL CHARACTERISTICS (T = -40 C to +85 C, V
A DD_DAC
= 5 V, VREF = 2.5 V, unless otherwise noted.)
Max Unit
Parameter STATIC PERFORMANCE Resolution Relative Accuracy, INL Differential Nonlinearity Gain Error Gain Error Temperature Coefficient Zero Code Error Zero Code Temperature Coefficient OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Digital-to-Analog Glitch Impulse Digital Feedthrough DAC Output Impedance Power Supply Rejection Ratio DAC REFERENCE INPUT Reference Input Range Reference Input Resistance* LOGIC INPUTS Input Current VINL, Input Low Voltage VINH, Input High Voltage Input Capacitance Hysteresis Voltage REFERENCE Reference -3 dB Bandwidth Reference Feedthrough Signal-to-Noise Ratio Reference Input Capacitance POWER REQUIREMENTS VDD IDD Power Dissipation
Condition 1 LSB = VREF/214 = 153 mV when VREF = 2.5 V Guaranteed Monotonic
Min
Typ
14
-1.75 0
0.15 0.15 -0.3 0.1 0.1 0.05
1.0 0.8 0 0.5
Bits LSB LSB LSB ppm/C LSB ppm/C V ms nV-s nV-s kW LSB V kW mA V V pF V MHz mV p-p dB pF pF
0 To 1/2 LSB of FS, CL = 10 pF 1 LSB Change around the Major Carry All 1s Loaded to DAC, VREF = 2.5 V Tolerance Typically 20% DVDD 10% 2 9 1 10 0.05 6.25
VREF -1 LSB
1.0 VDD
1.0 0.8 2.4 10 0.4 All 1s Loaded All 0s Loaded, VREF = 1 V p-p at 100 kHz Code 0000H Code 3FFFH 4.5 0.3 1.5 1.3 1 92 75 120 5.50 1.1 6.05
V mA mW
*Reference input resistance is code-dependent, minimum at 2555 H. Specifications subject to change without notice.
-6-
REV. A
AD15700 14-BIT DAC TIMING CHARACTERISTICS1, 2 T = T
Parameter
fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
(VDD = 5 V, 5%, VREF = 2.5 V, AGND = DGND = 0 V. All Specifications A MIN to TMAX, unless otherwise noted).
Unit
MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
Limit at TMIN, TMAX All Versions
25 40 20 20 15 15 35 20 15 0 30
Description
SCLK Cycle Frequency SCLK Cycle Time SCLK High Time SCLK Low Time CS_DAC Low to SCLK High Setup CS_DAC High to SCLK High Setup SCLK High to CS_DAC Low Hold Time SCLK High to CS_DAC High Hold Time Data Setup Time Data Hold Time CS_DAC High Time between Active Periods
NOTES 1 Guaranteed by design. Not production tested. 2 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90% of 3 V and timed from a voltage level of 1.6 V). Specifications subject to change without notice.
t1
SCLK
t6 t4
CS_DAC
t2
t3 t7
t5
t10 t8 t9
DIN
DB13
DB0
Figure 3. Timing Diagram
REV. A
-7-
AD15700 AMPLIFIER ELECTRICAL CHARACTERISTICS unless otherwise noted.)]
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Slew Rate Settling Time to 0.1% Condition G = +1, VO < 0.4 V p-p G = -1, VO = 2 V Step G = -1, VO = 2 V Step, CL = 10 pF
[5 V Supply (TA = 25 C, VS = 5 V, RL = 1 k to 2.5 V, RF = 2.5 k ,
Min 54 27 Typ 80 32 125 -62 -86 15 2.4 5 0.17 0.11 1 6 5 0.45 50 82 6 10 1.2 2.0 350 Max Unit MHz V/ms ns dBc dBc nV//Hz pA//Hz pA//Hz % Degrees mV mV mV/C mA mA nA dB dB MW kW pF V V dB dB V V V V V mA mA mA pF 12 1400 V mA dB C
DISTORTION/NOISE PERFORMANCE Total Harmonic Distortion fC = 1 MHz, VO = 2 V p-p, G = +2 fC = 100 kHz, VO = 2 V p-p, G = +2 Input Voltage Noise f = 1 kHz Input Current Noise f = 100 kHz f = 1 kHz Differential Gain RL = 1 kW Differential Phase RL = 1 kW DC PERFORMANCE Input Offset Voltage Offset Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Resistance Differential Input Resistance Input Capacitance Input Voltage Range Input Common-Mode Voltage Range Common-Mode Rejection Ratio Differential/Input Voltage OUTPUT CHARACTERISTICS Output Voltage Swing Low Output Voltage Swing High Output Voltage Swing Low Output Voltage Swing High Output Current Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE
Specifications subject to change without notice.
VCM = VCC/2; VOUT = 2.5 V TMIN to TMAX VCM = VCC/2; VOUT = 2.5 V VCM = VCC/2; VOUT = 2.5 V TMIN to TMAX VCM = VCC/2; VOUT = 1.5 V to 3.5 V TMIN to TMAX 76 74
VCM = 0 V to 5 V VCM = 0 V to 3.8 V
56 66
40 280 1.6 -0.5 to +5.5 -0.2 to +5.2 70 80 3.4 0.02 4.98 0.1 4.9 15 28 -46 15
RL = 10 kW RL = 1 kW
0.05 4.95 0.2 4.8
Sourcing Sinking G = +2 2.7 VS- = 0 V to -1 V or VS+ = 5 V to 6 V 75 -40
800 86
+85
-8-
REV. A
AD15700 AMPLIFIER ELECTRICAL CHARACTERISTICS unless otherwise noted.)]
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Slew Rate Settling Time to 0.1% DISTORTION/NOISE PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Differential Phase DC PERFORMANCE Input Offset Voltage Offset Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Resistance Differential Input Resistance Input Capacitance Input Voltage Range Input Common-Mode Voltage Range Common-Mode Rejection Ratio Differential/Input Voltage OUTPUT CHARACTERISTICS Output Voltage Swing Low Output Voltage Swing High Output Voltage Swing Low Output Voltage Swing High Output Current Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE
Specifications subject to change without notice.
[ 5 V Supply (TA = 25 C, VS = 5 V, RL = 1 k
Min 54 30 Typ 80 35 125 -62 -86 15 2.4 5 0.15 0.15 1 6 5 0.45 50 80
to 0 V, RF = 2.5 k ,
Max Unit MHz V/ms ns dBc dBc nV//Hz pA//Hz pA//Hz % Degrees 6 10 1.2 2.0 350 mV mV mV/C mA mA nA dB dB MW kW pF V V dB dB V V V V V mA mA mA pF 6 1600 V mA dB C
Condition G = +1, VO < 0.4 V p-p G = -1, VO = 2 V Step G = -1, VO = 2 V Step, CL = 10 pF fC = 1 MHz, VO = 2 V p-p, G = +2 fC = 100 kHz, VO = 2 V p-p, G = +2 f = 1 kHz f = 100 kHz f = 1 kHz RL = 1 kW RL = 1 kW VCM = 0 V; VOUT = 0 V TMIN to TMAX VCM = 0 V; VOUT = 0 V VCM = 0 V; VOUT = 0 V TMIN to TMAX VCM = 0 V; VOUT = 2 V TMIN to TMAX
76 74
VCM = -5 V to +5 V VCM = -5 V to +3.5 V
60 66
40 280 1.6 -5.5 to +5.5 -5.2 to +5.2 80 90 3.4 -4.98 +4.98 -4.85 +4.75 15 +35 -50 15
RL = 10 kW RL = 1 kW
-4.94 +4.94 -4.7 +4.7
Sourcing Sinking G = +2 1.35 VS- = -5 V to -6 V or VS+ = +5 V to +6 V 76 -40
900 86
+85
REV. A
-9-
AD15700
RESISTOR DIVIDER ELECTRICAL CHARACTERISTICS (@ T = 25 C, unless otherwise noted.)
A
Parameter Resistance Temperature Coefficient of Resistance Resistance Ratio of Two Halves Resistance Ratio Tracking Power Dissipation
Condition
Min 2.97 0.99
Typ 3.00 50 1.0
Max 3.03 1.01 2 250*
Unit kW ppm/C ppm/C mW
TA = 70C
*At higher temperatures, linearly derates to 0 mW at 175C. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS* Analog Inputs IND, INC, INB . . . . . . . . . . . . . . . . . . . . . . -11 V to +30 V INA, REF, INGND, REFGND, AGND . . . -0.3 V to AVDD + 0.3 V ADC Ground Voltage Differences AGND_ADC, DGND_ADC, OGND . . . . . . . . . . . . 0.3 V ADC Supply Voltages AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . 7 V DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V ADC Digital Inputs . . . . . . . . . . . . . -0.3 V to DVDD + 0.3 V VDD_DAC to AGND_DAC . . . . . . . . . . . . . . . -0.3 V to +6 V DAC Digital Input Voltage to DGND_DAC . . . . . . . . . . . . . . . . -0.3 V to DVDD + 0.3 V VOUT_DAC to AGND_DAC . . . . -0.3 V to DVDD + 0.3 V AGND_DAC to DGND_DAC . . . . . . . . . . . -0.3 V to +0.3 V DAC Input Current to Any DAC Pin Except Supplies . . 10 mA
Amplifier Supply Voltage (VS1, VS2) . . . . . . . . . . . . . . 12.6 V Amplifier Input Voltage (Common Mode) . . . . . . VS 0.5 V Amplifier Differential Input Voltage . . . . . . . . . . . . . . . 3.4 V Amplifier Output Short Circuit Duration . . . . . . . . . . . . . . Observe Power Derating Curves Resistor Instantaneous Voltage Drop . . . . . . . . . . . . . . . 50 V Internal Power Dissipation . . . . . . . . . . . . . (TJ Max - TA)/ JA Thermal Resistance JA 10 mm CSPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . 42C/W Maximum Junction Temperature (TJ Max) . . . . . . . . . . 150C Operating Temperature Range . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . 225C, 15 sec
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD15700BCA AD15700/PCB ADDS-2191-EZLITETM ADDS-21535-EZLITE ADDS-21160M-EZLITE ADDS-21161N-EZLITE
Temperature Range -40C to +85C 25C 25C
Package Option 144-Lead CSPBGA Evaluation Board Evaluation Kit*
*One of the DSP Evaluation Kits is required for operation of the AD15700/PCB Evaluation Board.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD15700 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
-10-
REV. A
AD15700
ADC PIN FUNCTION DESCRIPTIONS (See Pinout, page 42)
Pin No. H9, J8, J9, M12 M6 L7
Mnemonic AGND_ADC AVDD BYTESWAP
Type P P DI
Description Analog Power Ground Pin Input Analog Power Pin. Nominally 5 V. Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the Serial Interface Mode is selected and some bits of the DATA bus are used as a serial port. Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the serial master read DIVSCLK[0:1] after Convert Mode. These inputs, part of the Serial Port, are used to slow down, if desired, the internal serial clock that clocks the data output. In the other serial modes, these inputs are not used. When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input for choosing the internal or an external data clock, called, respectively, Master and Slave Mode. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input and the external clock is gated by CS_ADC. When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal. It is active in both Master and Slave Mode. When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input, depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. Input/Output Interface Digital Power Ground Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (5 V or 3.3 V). Digital Power. Nominally at 5 V.
L8
OB/2C
DI
M7
WARP
DI
L9 M8
IMPULSE SER/PAR
DI DI
M9, L10
D[0:1]
DO DI/O
M10, L11 D[2:3] or DIVSCLK[0:1]
M11
D[4] or EXT/INT
DI/O
L12
D[5] or INVSYNC
DI/O
K11
D[6] or INVSCLK
DI/O
K12
D[7] or RDC/SDIN
DI/O
J10 J11 J12
OGND OVDD DVDD
P P P
REV. A
-11-
AD15700
ADC PIN FUNCTION DESCRIPTIONS (continued)
Pin No. H10 H12
Mnemonic DGND_ADC D[8] or SDOUT
Type P DO
Description Digital Power Ground When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The ADC provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In Serial Mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge. When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is High, SYNC is driven LOW and remains LOW while SDOUT output is valid. When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus. When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is used as an incomplete read error flag. In Slave Mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed high. Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. Must be Tied to Digital Ground Read Data. When CS_ADC and RD are both LOW, the interface parallel or serial output bus is enabled. Chip Select. When CS_ADC and RD are both LOW, the interface parallel or serial output bus is enabled. CS_ADC is also used to gate the external serial clock. Reset Input. When set to a logic HIGH, reset the ADC. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND. Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW), if CNVST is held low when the acquisition phase (t8) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. Must be Tied to Analog Ground Reference Input Voltage Reference Input Analog Ground Analog Input Ground Analog Inputs. Refer to Table I for input range configuration.
H11
D[9] or SCLK
DI/O
G12
D[10] or SYNC
DO
G11
D[11] or RDERROR
DO
F12, F11, D[12:15] E12, E11 G10 BUSY
DO DO
G9 E10 K10 D12 K9 E7
DGND_ADC RD CS_ADC RESET PD CNVST
P DI DI DI DI DI
H8 G5 H5 J7 J5, K5, L5, M5
AGND_ADC REF REFGND INGND INA, INB, INC, IND
P AI AI P AI
-12-
REV. A
AD15700
DAC PIN FUNCTION DESCRIPTIONS
Pin No. A6 A3, C3, C4 A2 B1 E1 E2 E3 C6
Mnemonic VOUT_DAC AGND_DAC VREF CS_DAC SCLK DIN DGND_DAC VDD_DAC
Type AO P AI DI DI DI P P
Description Analog Output Voltage from the DAC Ground Reference Point for Analog Circuitry This is the voltage reference input for the DAC. Connect to external reference ranges from 2 V to VDD. This is an active low logic input signal. The chip select signal is used to frame the serial data input. Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK. Digital Ground. Ground reference for digital circuitry. Analog Supply Voltage, 5 V 10%
AMPLIFIER PIN FUNCTION DESCRIPTIONS
Pin No. C9 (J1) A9 (G1) B12 (K4) A11 (F3) B10, B11 (G3, H3)
Mnemonic +IN1(2) -IN1(2) VOUT1(2) +VS1(2) -VS1(2)
Type AI AI AO P P
Description Positive Input Voltage Negative Input Voltage Amplifier Output Voltage Analog Positive Supply Voltage Analog Negative Supply Voltage
RESISTOR PIN FUNCTION DESCRIPTIONS
Pin No. B9 (L4) A8 (M4) D9 (L1) A7 (M3)
Mnemonic RA1(2) RB1(2) RC1(2) RPAD1(2)
Type AI/O AI/O AI/O P
Description Resistor End Terminal Resistor Center Tap Resistor End Terminal Resistor Die Pad. Tie to Analog Ground.
COMMON PIN FUNCTION DESCRIPTIONS
Pin No. A1, A4, A5, A10, A12, B2-B8, C1, C2, C5, C7, C8, C10-C12, D1-D8, D10, D11, E4-E6, E8, E9, F1, F2, F4-F10, G2, G4, G6-G8, H1, H2, H4, H6, H7, J2-J4, J6, K1-K3, K6-K8, L2, L3, L6, M1, M2
NOTES AI = Analog Input AI/O = Bidirectional Analog AO = Analog Output DI = Digital Input DI/O = Bidirectional Digital DO = Digital Output P = Power
Mnemonic COMMON
Type P
Description Common Floating Net Connecting 69 Pins. Not electrically connected within the module. Tie at least one of these pins to Analog Ground.
REV. A
-13-
AD15700
ADC DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) DAC DEFINITION OF SPECIFICATIONS Relative Accuracy
Linearity error refers to the deviation of each individual code from a line drawn from "negative full scale" through "positive full scale." The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. A typical INL versus code plot can be seen in TPC 16.
Differential Nonlinearity
In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.
Full-Scale Error
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. TPC 19 illustrates a typical DNL versus code plot.
Gain Error
The last transition (from 011...10 to 011...11 in twos complement coding) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (2.499886 V for the 2.5 V range). The full-scale error is the deviation of the actual level of the last transition from the ideal level.
Bipolar Zero Error
Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal.
Gain Error Temperature Coefficient
This is a measure of the change in gain error with changes in temperature. It is expressed in ppm/C.
Zero Code Error
The difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code.
Unipolar Zero Error
Zero code error is a measure of the output error when zero code is loaded to the DAC register.
Zero Code Temperature Coefficient
In unipolar mode, the first transition should occur at a level 1/2 LSB above analog ground. The unipolar zero error is the deviation of the actual transition from that point.
Spurious Free Dynamic Range (SFDR)
This is a measure of the change in zero code error with a change in temperature. It is expressed in mV/C.
Digital-to-Analog Glitch Impulse
The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
A measurement of the resolution with a sine wave input. It is related to S/(N + D) by the following formula: ENOB = S / N + D and is expressed in bits.
Total Harmonic Distortion (THD)
((
[
]
dB
- 1.76 / 6.02
)
)
Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition. A plot of the glitch impulse is shown in Figure 28.
Digital Feedthrough
The rms sum of the first five harmonic components to the rms value of a full-scale input signal; expressed in decibels.
Signal-to-Noise Ratio (SNR)
The ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (S/[N + D])
Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. CS_DAC is held high, while the CLK and DIN signals are toggled. It is specified in nV-s and is measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. A typical plot of digital feedthrough is shown in Figure 27.
Power Supply Rejection Ratio
The ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N + D) is expressed in decibels.
Aperture Delay
This specification indicates how the output of the DAC is affected by changes in the power supply voltage. Power supply rejection ratio is quoted in terms of percent change in output per percent change in VDD for full-scale output of the DAC. VDD is varied by 10%.
Reference Feedthrough
A measure of the acquisition performance, measured from the falling edge of the CNVST input to when the input signal is held for a conversion.
Transient Response
This is a measure of the feedthrough from the VREF input to the DAC output when the DAC is loaded with all 0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough is expressed in mV p-p.
The time required for the ADC to achieve its rated accuracy after a full-scale step function is applied to its input.
-14-
REV. A
Typical Performance Characteristics- AD15700
16-BIT D/A CONVERTER
2.5 2.0 1.5
NUMBER OF UNITS
60
50
1.0
40
INL - LSB
0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 0 16384 32768 CODE 49152 65536
30
20
10
0 -3.0 -2.7
-2.4
-2.1
-1.8 -1.5 -1.2 -0.9 NEGATIVE INL - LSB
-0.6
-0.3
0.0
TPC 1. Integral Nonlinearity vs. Code
TPC 4. Typical Negative INL Distribution (314 Units)
1.75 1.50 1.25 1.00 0.75
8000 7000 6000 5000 7029 7039
DNL - LSB
0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 0 16384 32768 CODE 49152 65536
COUNTS
4000 3000 2000 1297 1000 986
25 0 0 0 0 17 0 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006 8007 CODE IN HEXADECIMAL
TPC 2. Differential Nonlinearity vs. Code
TPC 5. Histogram of 16,384 Conversions of a DC Input at the Code Transition
60
10000
9503
9000
50
8000
NUMBER OF UNITS
40
7000
30
COUNTS
6000 5000 4000
3296 3344
20
3000 2000 1000
10
0 0.0
0.3
0
0
0
2
132
8001 8002
106
8003 8004
1
8005
0
8006
0
8007
0.6
0.9
1.2 1.5 1.8 2.1 POSITIVE INL - LSB
2.4
2.7
3.0
7FFC 7FFD 7FFE 7FFF 8000
CODE IN HEXADECIMAL
TPC 3. Typical Positive INL Distribution (314 Units)
TPC 6. Histogram of 16,384 Conversions of a DC Input at the Code Center
REV. A
-15-
AD15700
0 -20 FS = 1 MSPS fIN = 45.5322kHz SNR = 89.45dB THD = -100.05dB SFDR = 100.49dB SINAD = 89.1dB
96
-98
AMPLITUDE - dB of Full Scale
-40 -60
93
-100
SNR - dB
-80 -100 -120 -140 -160 -180 0 100 200 300 FREQUENCY - kHz 400 500
90
-102
87
-104
84 -55 -35 -15 5 25 45 65 TEMPERATURE - C 85 105 125
-106
TPC 7. FFT Plot
TPC 10. SNR, THD vs. Temperature
100
16.0
-60 -65 SFDR -70
THD, HARMONICS - dB
115 110 105 100 95 90 85 SECOND HARMONIC THD 80 75 70 65 THIRD HARMONIC 1 10 100 FREQUENCY - kHz 60 1000
SFDR - dB
95 SNR AND S/[N + D] - dB SNR 90 SINAD 85 ENOB 80
15.5
-75 -80 -85 -90 -95 -100 -105 -110
15.0 ENOB - Bits
14.5
14.0
75
13.5
70 0 10 100 FREQUENCY - kHz
13.0 1000
-115
TPC 8. SNR, S/(N + D), and ENOB vs. Frequency
TPC 11. THD, Harmonics, and SFDR vs. Frequency
100
16.0
-60 -70
95 SNR AND S/[N + D] - dB SNR 90 SINAD 85 ENOB 80
15.5 -80 15.0 ENOB - Bits
THD, HARMONICS - dB
-90 -100 SECOND HARMONIC -110 -120 -130 THD
14.5
14.0
75
13.5 -140 THIRD HARMONIC
70 1 10 100 FREQUENCY - kHz
13.0 1000
-150 -60
-50
-40 -30 -20 INPUT LEVEL - dB
-10
0
TPC 9. SNR vs. Input Frequency
TPC 12. THD, Harmonics vs. Input Level
-16-
REV. A
THD - dB
AD15700
50
POWER-DOWN OPERATING CURRENTS - nA
1000 900 800 700 DVDD 600 500 400 OVDD 300 200 AVDD 100 0 -55 -35 -15 45 5 25 TEMPERATURE - C 65 85 105
40
t12 DELAY - ns
30
20
10
0 0 50 100 CL - pF 150 200
TPC 13. Typical Delay vs. Load Capacitance CL
TPC 15. Power-Down Operating Currents vs. Temperature
100000 AVDD, WARP/NORMAL 10000 DVDD, WARP/NORMAL 1000 100 10 0 0.1 0.01 0.001 0 10 1000 10000 100 SAMPLING RATE - SPS 100000 1000000 OVDD, ALL MODES AVDD, IMPULSE DVDD, IMPULSE
OPERATING CURRENTS - mA
TPC 14. Operating Currents vs. Sample Rate
REV. A
-17-
AD15700
14-BIT D/A CONVERTER
0.50 TA = 25 C VDD = 5V VREF = 2.5V 0.25 0.25 0.50 TA = 25 C VDD = 5V VREF = 2.5V
0
DNL - LSB
2048
INL - LSB
0
-0.25
-0.25
-0.50 0 4096 6144 8192 10240 CODE - Decimal 12288 14336 16384
-0.50 0 2048 4096 6144 8192 10240 CODE - Decimal 12288 14336 16384
TPC 16. Integral Nonlinearity vs. Code
TPC 19. Differential Nonlinearity vs. Code
0.50 VDD = 5V VREF = 2.5V 0.25
0.50 VDD = 5V VREF = 2.5V 0.25
DNL - LSB
INL - LSB
0
0
-0.25
-0.25
-0.50 -60 -20 20 60 TEMPERATURE - C 100 140
-0.50 -60 -20 20 60 TEMPERATURE - C 100 140
TPC 17. Integral Nonlinearity vs. Temperature
TPC 20. Differential Nonlinearity vs. Temperature
1.00 0.75 VDD = 2.5V TA = 25 C
0.50 VDD = 5V TA = 25 C DNL LINEARITY ERROR - LSB 0.25
LINEARITY ERROR - LSB
0.50 0.25 0 -0.25 -0.50
DNL
0
-0.25 INL
INL -0.75 -1.00 2 3 4 5 6 7 SUPPLY VOLTAGE - V
-0.50 0 1
2 3 4 REFERENCE VOLTAGE - V
5
6
TPC 18. Linearity Error vs. Supply Voltage
TPC 21. Linearity Error vs. Reference Voltage
-18-
REV. A
AD15700
1.00 0.75 0.50 GAIN ERROR - LSB 0.25 0 -0.25 -0.50 -0.75 -1.00 -50 VDD = 5V VREF = 2.5V
0.75 VDD = 5V VREF = 2.5V
ZERO-CODE OFFSET ERROR - LSB
-25 0 25 50 75 TEMPERATURE - C 100 125 150
0.50
0.25
0 -50
-25
0
25
50
75
100
125
150
TEMPERATURE - C
TPC 22. Gain Error vs. Temperature
TPC 25. Zero-Code Error vs. Temperature
250 VDD = 5V VLOGIC = 5V VREF = 2.5V
450 TA = 25 C 400 SUPPLY CURRENT - mA
SUPPLY CURRENT - mA
350 SUPPLY VOLTAGE VREF = 2.5V REFERENCE VOLTAGE VDD = 5V
200
300
250
200
150 -40
150 -20 0 20 40 60 TEMPERATURE - C 80 100 120 0 1 2 3 VOLTAGE - V 4 5 6
TPC 23. Supply Current vs. Temperature
TPC 26. Supply Current vs. Reference Voltage or Supply Voltage
400 VDD = 5V VREF = 2.5V TA = 25 C REFERENCE CURRENT - mA
300 TA = 25 C VDD = 5V VREF = 2.5V
350
250
SUPPLY CURRENT - mA
200
300
150
250
100
200
50
150 0 1 2 3 DIGITAL INPUT VOLTAGE - V 4 5
0 0 2048 4096 8192 10240 6144 CODE - Decimal 12288 14336 16384
TPC 24. Supply Current vs. Digital Input Voltage
TPC 27. Reference Current vs. Code
REV. A
-19-
AD15700
90 80 N = 250
INPUT BIAS CURRENT - nA NUMBER OF PARTS IN BIN 800 600 400 200 0 VS = 2.7V -200 -400 -600 -800 VS = 5V VS = 10V
70 60 50 40 30 20 10 0 -5 -4 -3 -2 -1 0 1 VDS - mV 2 3 4 5 6
0
1
2
4 5 6 3 7 COMMON-MODE VOLTAGE - V
8
9
10
TPC 28. Typical VOS Distribution @ VS = 5 V
TPC 31. Input Bias Current vs. Common-Mode Voltage
2.5
0
2.3
OFFSET VOLTAGE - mV OFFSET VOLTAGE - mV
-0.1
-0.2 VS = 5V -0.3
2.1 VS = 5V
1.9 VS = 65V 1.7
-0.4
-0.5
1.5 -40 -30 -20 -10
-0.6 0 10 20 30 40 50 TEMPERATURE - C 60 70 80 90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 COMMON-MODE VOLTAGE - V 4.0 4.5 5.0
TPC 29. Input Offset Voltage vs. Temperature
TPC 32. VOS vs. Common-Mode Voltage
1.00 0.95 0.90 VS = 5V
INPUT BIAS - mA
1000 950 900 850 800 750 700 650 600 -40 -30 -20 -10 IS = 2.7V IS = 5V IS = 5V
0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 -40 -30 -20 -10 0 10 20 30 40 50 TEMPERATURE - C 60 70 80 90
SUPPLY CURRENT/AMPLIFIER - mA
0
10 20 30 40 50 TEMPERATURE - C
60
70
80
90
TPC 30. Input Bias Current vs. Temperature
TPC 33. Supply Current vs. Temperature
-20-
REV. A
AD15700
AMPLIFIER
0 1.2 VCC = 2.7V VCC = 10V VCC VOUT VIN 0.8 VEE RLOAD VCC 2 1.0
DIFFERENCE FROM V CC - V
VCC = 5V -1.0
DIFFERENCE FROM VEE - V
-0.5
0.6 VCC = 5V 0.4
VCC -1.5 VIN VEE VOUT VCC = 10V RLOAD VCC 2 10k
-2.0
0.2 VCC = 2.7V 100 1k RLOAD - 10k
-2.5 100 1k RLOAD -
0
TPC 34. +Output Saturation Voltage vs. RLOAD @ 85C
TPC 37. -Output Saturation Voltage vs. RLOAD @ 85C
0
VCC = 2.7V
1.2
VCC = 10V
VCC
VOUT
DIFFERENCE FROM V CC - V
DIFFERENCE FROM VEE - V
-0.5
1.0
VIN
VCC = 5V -1.0 VCC -1.5 VIN VEE VOUT VCC = 10V RLOAD VCC 2 10k
0.8
RLOAD
VEE
0.6
VCC = 5V
VCC 2
0.4
-2.0
0.2
-2.5 100
0
VCC = 2.7V
1k RLOAD -
100
1k RLOAD -
10k
TPC 35. +Output Saturation Voltage vs. RLOAD @ 25C
TPC 38. -Output Saturation Voltage vs. RLOAD @ 25C
0
VCC = 2.7V
1.2 VCC = 10V VCC VOUT VIN 0.8 VEE RLOAD VCC 2
DIFFERENCE FROM V CC - V
VCC = 5V -1.0 VCC -1.5 VIN VEE VOUT VCC = 10V RLOAD VCC 2 10k
DIFFERENCE FROM VEE - V
-0.5
1.0
0.6 VCC = 5V 0.4
-2.0
0.2 VCC = 2.7V 100 1k RLOAD - 10k
-2.5 100 1k RLOAD -
0
TPC. 36 +Output Saturation Voltage vs. RLOAD @ -40C
TPC. 39 -Output Saturation Voltage vs. RLOAD @ -40C
REV. A
-21-
AD15700
110 VS = 5V 105 -AOL
INPUT BIAS CURRENT - mA 500mV
100
1V
100 95 GAIN - dB 90 85
10
90
0
+AOL 80 75 70 65 60 0 2k 4k RLOAD - 6k 8k 10k
VS = 5V -10
10 0%
500mV
-1.5
0.5 2.5 4.5 INPUT VOLTAGE - V
6.5
TPC 40. Open-Loop Gain (AOL) vs. RLOAD
TPC 43. Differential Input Voltage 1 V Characteristics
86
DIFF GAIN - %
0.05
VS = 5V RL = 1k
0.00 -0.05 -0.10 -0.15
84
-AOL
GAIN - dB
82
+AOL
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
80
DIFF PHASE - Degrees
0.10 0.05 0.00 -0.05 -0.10
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
78
76 -40 -30 -20 -10
0
10 20 30 40 50 TEMPERATURE - C
60
70
80
90
TPC 41. Open-Loop Gain (AOL) vs. Temperature
TPC 44. Differential Gain and Phase @ VS = 5 V; RL = 1 kW
110 RLOAD = 10k 100 VS = 5V
INPUT VOLTAGE NOISE - nV/ Hz
100 VS = 5V 30 VOLTAGE NOISE 10 10 100
INPUT CURRENT NOISE - pA/ Hz
90
AOL - dB
RLOAD = 1k 80
3 CURRENT NOISE 1
1
70
60
0.1
50 0 0.5 1.0 1.5 2.0 2.5 3.0 VOUT - V 3.5 4.0 4.5 5.0
0.3 10 100 1k 10k 100k 1M 10M FREQUENCY - Hz
TPC 42. Open-Loop Gain (AOL) vs. VOUT
TPC 45. Input Voltage Noise vs. Frequency
-22-
REV. A
AD15700
5 4 3
NORMALIZED GAIN - dB
30 20 10 0
2 1 0
PHASE - Degree
-1 -2 -3 -4 -5 0.1 1 10 FREQUENCY - MHz 100
-90 PHASE -135 -180 -225 0.3 1 10 FREQUENCY - MHz 100
-10 -20
TPC 46. Unity Gain, -3 dB Bandwidth
TPC 49. Open-Loop Frequency Response
3 TOTAL HARMONIC DISTORTION - dBc 2 NORMALIZED GAIN - dB 1 0 -1 -2 -3 -4 -5 0.1 1 10 FREQUENCY - MHz 100 VS 2k VIN VOUT 50 +25 C VS = 5V VIN = -16dBm +85 C -40 C
-20
-30 G = +1, RL = 2k -40 1.3V p-p VS = 2.7V -50 2.5V p-p VS = 2.7V -60 2V p-p VS = 2.7V -70 4.8V p-p VS = 5V -80 1k 100k 1M 10k FUNDAMENTAL FREQUENCY - Hz 10M TO VCC 2
TPC 47. Closed-Loop Gain vs. Temperature
TPC 50. Total Harmonic Distortion vs. Frequency; G = +1
2 1 0
TOTAL HARMONIC DISTORTION - dBc
VS = -2.7V RL + CL TO 1.35V VS = 65V
VS = 5V RL + CL TO 2.5V
-20 -30 -40 -50 -60 -70 -80 -90 -100 1k 100k 1M 10k FUNDAMENTAL FREQUENCY - Hz 10M 4.6V p-p 4V p-p G = +2 VS = 5V VCC RL = 1k TO 2 4.8V p-p 1V p-p
CLOSED-LOOP GAIN - dB
-1 -2 -3 -4 -5 -6 -7 -8 10k 1M G = +1 CL = 5pF RL = 1k
10M FREQUENCY - Hz
100M
TPC 48. Closed-Loop Gain vs. Supply Voltage
TPC 51. Total Harmonic Distortion vs. Frequency; G = +2
REV. A
-23-
OPEN-LOOP GAIN - dB
VS = 5V G = +1 RL = 1k
40 GAIN
AD15700
10
POWER SUPPLY REJECTION RATIO - dB
0
VS = 65V 8
-20
VS = 5V
-40
OUTPUT - V p-p
6
-60
4
VS = 5V
-80
2
VS = 2.7V
-100
0 1k 100k 1M 10k FUNDAMENTAL FREQUENCY - Hz 10M
-120 100 1k 100k 1M 10k FREQUENCY - Hz 10M 100M
TPC 52. Large Signal Response
TPC 55. PSRR vs. Frequency
100 50
RBT = 50
5.5 4.5
VS = 5V RL = 10k TO 2.5V VIN = 6V p-p G = +1
ROUT -
1V/DIV
10
3.5 2.5 1.5 0.5
1
RB- VOUT RBT = 0
0.1
-0.5
0.1
1 10 FREQUENCY - MHz
100 200
10 s/DIV
TPC 53. ROUT vs. Frequency
TPC 56. Output Voltage
0
COMMON-MODE REJECTION RATIO - dB
VS = 5V -20 5.5 4.5
INPUT
VS = 5V G = +1 INPUT = 650mV BEYOND RAILS
1V/DIV
100 1k 100k 10k FREQUENCY - Hz 1M 10M
-40
3.5 2.5 1.5 0.5
-60
-80
-0.5
-100 10 s/DIV
TPC 54. CMRR vs. Frequency
TPC 57. Output Voltage Phase Reversal Behavior
-24-
REV. A
AD15700
RL TO 2.5V 2.85 2.35 VS = 27V RL = 1k G = -1
500mV/DIV
500mV/DIV
1.85 1.35 0.85 0.35 RL TO 1.35V
RL TO GND 0 10 s/DIV
VS = 5V RL = 1kV G = -1
RL TO GND
10 s/DIV
TPC 58. Output Swing
TPC 60. Output Swing
3.1 2.9
G = +2 RF = RG = 2.5k RL = 2k CL = 5pF VS = 5V
2.56 2.54
G = +1 RF = 0 RL = 2k TO 2.5V CL = 5pF TO 2.5V VS = 5V
200mV/DIV
2.5 2.3 2.1 1.9
20mV/DIV
50ns/DIV
2.7
2.52 2.50 2.48 2.46 2.44
50ns/DIV
TPC 59. 1 V Step Response
TPC 61. 100 mV Step Response
REV. A
-25-
AD15700
CIRCUIT OPERATION TYPICAL CONNECTION DIAGRAM
The AD15700 contains precision components for interfacing analog I/O to a processor. Configuration for particular applications can be made with short external interconnects under the device.
Figure 4 shows how, using a minimum of external devices, the components within the AD15700 can be interconnected to form a complete analog interface to a processor. The circuit implements signal conditioning that includes buffering, filtering, and voltage scaling.
AD15700
ANALOG INPUT (0.2V TO 2REF) +IN2 -IN2 OP-AMP VOUT2 +VS2 -VS2 +VS STATE MACHINE
C2 NOTE 2
RA2 RB2 RC2 INA INB INC IND INGND
RESISTOR RPAD2 ADC RFS TFS RCLK TCLK
SCLK CNVST SDOUT BUSY OB/2C SER/PAR WARP RDC/SIN INVSCLK INVSYNC EXT/INT DIVSCLK1 DIVSCLK0 IMPULSE CS_ADC RD BYTESWAP RESET PD DVDD
DSP/ P
ADR421 OR AD780 2.5V OR 3.0V REF
47 F ANALOG SUPPLY (5V)
0.1 F
REF REFGND
0.1 F AGND
100 0.1 F
AVDD AGND_ADC DVDD DGND_ADC OVDD OGND DAC
10 F
DIGITAL SUPPLY (3.3V OR 5V)
0.1 F
DGND
VREF VDD_DAC DGND_DAC AGND_DAC VOUT_DAC RA1 RB1 RC1 +IN1 -IN1 C1 NOTE 1
SCLK CS_DAC DIN
RESISTOR RPAD1 OP AMP
+VS1 -VS1 VOUT1
+VS 0.1 F
ANALOG OUTPUT (0.2V TO 2REF)
NOTES 1. C1 FORMS AN R-C FILTER WITH THE 6.25k NOMINAL OUTPUT RESISTANCE OF THE DAC 2. C2 FORMS PART OF THE ADC INPUT FILTER. SEE ANALOG INPUT SECTION.
Figure 4. Typical Connection Diagram
-26-
REV. A
AD15700
Analog Input Section Processor Interface
Made up of a buffer amplifier, an RC filter, and an ADC, the analog input circuit allows measurement of voltages ranging from 0.2 V to 2 REF V. When placed in the 0 V to REF input range, the circuit has the configuration shown in Figure 5a.
ANALOG INPUT ADC 1.5k 1.5k C2 277 60pF
Figure 5a. Analog Input Circuit
The filter is made up of one of the AD15700's internal centertapped resistors, an external capacitor C2, plus the ADC's internal resistance and capacitance. The transfer function of this filter is given by:
The circuit in Figure 5a uses serial interfacing to minimize the number of signals that connect to the digital circuits. External logic such as a state machine is used to generate clocks and other timing signals for the interface. Ideally, the clocks supplied to the converters are discontinuous and operate at the maximum frequency supported by the converter and the processor. Discontinuous clocks that are quiet during critical times minimize degradation caused by voltage transients on the digital interface. It is best to keep the clocks quiet during ADC conversion and when the DAC output is sampled by the external system. Often, the processor cannot tolerate a discontinuous clock and therefore a separate continuous clock (or clocks) that is synchronous with the converter clocks must be generated. Separate clocks for the DAC and ADC are used to maximize the data transfer rate to each converter. The ADC operates at a maximum rate of 40 MHz while the DAC can operate up to 25 MHz.
ADC CIRCUIT INFORMATION
H (s ) =
8.11425 106 1.62285 10 + 202.288 s 2C 2 + s + 1.21714 1010 sC 2
7
With C2 set to 100 pF, the bandwidth is 1.2 MHz. Without C2, the bandwidth of the filter is 2.6 MHz. To utilize the ADC's maximum 9.6 MHz bandwidth, the components external to the ADC are eliminated. In this case, the ADC is configured for its 0 to 2 REF input range and the resulting equivalent input circuit is shown in Figure 5b.
ANALOG INPUT 375 375 ADC 100 60pF
The ADC is a fast, low power, single-supply precise 16-bit analogto-digital converter (ADC). It features different modes to optimize performances according to the applications. In warp mode, it is capable of converting 1,000,000 samples per second (1 MSPS). The ADC provides the user with an on-chip track/hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. It is specified to operate with both bipolar and unipolar input ranges by changing the connection of its input resistive scaler. The ADC can be operated from a single 5 V supply and be interfaced to either 5 V or 3 V digital logic.
Figure 5b. Analog Input Circuit
Analog Output Section ADC CONVERTER OPERATION
The output circuitry consists of a DAC, RC filter, and an amplifier. The circuit uses the DAC's output resistance of 6.25 kW 20% to form a single-pole RC filter with an external capacitor C1. One of the AD15700's internal center-tapped resistors and one of its op amps form an amplifier with a gain of two. The gain is used to bring the DAC's maximum range of REF volts up to 2 REF V.
DAC 6.25k C1 1.5k 1.5k ANALOG OUTPUT
The ADC is a successive approximation analog-to-digital converter based on a charge redistribution DAC. Figure 7 shows the simplified schematic of the ADC. The input analog signal is first scaled down and level-shifted by the internal input resistive scaler, which allows both unipolar ranges (0 V to 2.5 V, 0 V to 5 V, and 0 to 10 V) and bipolar ranges ( 2.5 V, 5 V, and 10 V). The output voltage range of the resistive scaler is always 0 V to 2.5 V. The capacitive DAC consists of an array of 16 binary weighted capacitors and an additional LSB capacitor. The comparator's negative input is connected to a "dummy" capacitor of the same value as the capacitive DAC array. During the acquisition phase, the common terminal of the array tied to the comparator's positive input is connected to AGND via SWA. All independent switches are connected to the output of the resistive scaler. Thus, the capacitor array is used as a sampling capacitor and acquires the analog signal. Similarly, the dummy capacitor acquires the analog signal on INGND input. When the acquisition phase is complete, and the CNVST input goes or is low, a conversion phase is initiated. When the conversion phase begins, SWA and SWB are opened first. The capacitor array and the dummy capacitor are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the output of the resistive scaler and INGND captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced.
Figure 6. Analog Output Circuit
Voltage Reference Input
The AD15700 uses an external 2.5 V or 3.0 V voltage reference. Because of the dynamic input impedance of the A/D and the code dependent impedance of the D/A, the reference inputs must be driven by a low impedance source. Decoupling consisting of a parallel combination of 47 mF and 0.1 mF capacitors is recommended. Suitable references include the ADR421 for 2.5 V output and the AD780 for selectable 2.5 V or 3.0 V output. Both of these feature low noise and low temperature drift.
REV. A
-27-
AD15700
4R IND REF 4R INC 2R INB 32768C R INA COMP INGND 65536C SWB CNVST CONTROL LOGIC OUTPUT CODE 16384C 4C 2C C C BUSY REFGND SWITCHES CONTROL LSB SWA
MSB
Figure 7. ADC Simplified Schematic
By switching each element of the capacitor array between REFGND or REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4. . .VREF/65536). The control logic toggles these switches, starting with the MSB first, in order to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and brings BUSY output low.
Modes of Operation
in this mode is 666 kSPS. When operating at 100 SPS, for example, it typically consumes only 15 mW. This feature makes the ADC ideal for battery-powered applications.
Transfer Functions
Using the OB/2C digital input, the ADC offers two output codings: straight binary and twos complement. The ideal transfer characteristic for the ADC is shown in Figure 8 and Table III.
ADC CODE - Straight Binary
The ADC features three modes of operation: warp, normal, and impulse. Each of these modes is more suitable for specific applications. The warp mode allows the fastest conversion rate up to 1 MSPS. However, in this mode and this mode only, the full specified accuracy is guaranteed only when the time between conversion does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms, for instance, after power-up, the first conversion result should be ignored. This mode makes the ADC ideal for applications where both high accuracy and fast sample rate are required. The normal mode is the fastest mode (800 kSPS) without any limitation about the time between conversions. This mode makes the ADC ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. The impulse mode, the lowest power dissipation mode, allows power saving between conversions. The maximum throughput
111...111 111...110 111...101
000...010 000...001 000...000 -FS -FS + 1LSB +FS - 1LSB +FS - 1.5LSB ANALOG INPUT
-FS + 0.5LSB
Figure 8. ADC Ideal Transfer Function
Table III. Output Codes and Ideal Input Voltages
Digital Output Code
Description Full-Scale Range Least Significant Bit FSR -1 LSB Midscale +1 LSB Midscale Midscale -1 LSB -FSR +1 LSB -FSR 10 V 305.2 mV 9.999695 V 305.2 mV 0V -305.2 mV -9.999695 V -10 V 5 V 152.6 mV 4.999847 V 152.6 mV 0V -152.6 mV -4.999847 V -5 V
Analog Input 2.5 V 76.3 mV 2.499924 V 76.3 mV 0V -76.3 mV -2.499924 V -2.5 V 0 V to 10 V 152.6 mV 9.999847 V 5.000153 V 5V 4.999847 V 152.6 mV 0V 0 V to 5 V 76.3 mV 4.999924 V 2.570076 V 2.5 V 2.499924 V 76.3 mV 0V 0 V to 2.5 V 38.15 mV 2.499962 V 1.257038 V 1.25 V 1.249962 V 38.15 mV 0V
(Hexadecimal) Straight Twos Binary Complement
FFFF1 8001 8000 7FFF 0001 00002
7FFF1 0001 0000 FFFF 8001 80002
NOTES 1 This is also the code for an overrange analog input. 2 This is also the code for an underrange analog input.
-28-
REV. A
AD15700
Analog Inputs
The ADC is specified to operate with six full-scale analog input ranges. Connections required for each of the four analog inputs, IND, INC, INB, INA, and the resulting full-scale ranges are shown in Table I. The typical input impedance for each analog input range is also shown. Figure 9 shows a simplified analog input section of the ADC.
AVDD
The capacitor CS is typically 60 pF and is mainly the ADC sampling capacitor. This one-pole filter with a typical -3 dB cutoff frequency of 9.6 MHz reduces undesirable aliasing effects and limits the noise coming from the inputs.
75 70 65
CMRR - dB
60 55 50
4R IND 4 INC INB INA 2R R R1 CS
45 40
R = 1.28k
35 1 10 100 FREQUENCY - kHz 1000 10000
AGND
Figure 10. Analog Input CMRR vs. Frequency
Figure 9. Simplified Analog Input
The four resistors connected to the four analog inputs form a resistive scaler that scales down and shifts the analog input range to a common input range of 0 V to 2.5 V at the input of the switched capacitive ADC. By connecting the four inputs INA, INB, INC, and IND to the input signal itself, the ground, or a 2.5 V reference, other analog input ranges can be obtained. The diodes shown in Figure 9 provide ESD protection for the four analog inputs. The inputs INB, INC, and IND, have a high voltage protection (-11 V to +30 V) to allow wide input voltage range. Care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs including INA (0 V to 5 V). This will cause these diodes to become forward-biased and start conducting current. These diodes can handle a forward-biased current of 120 mA maximum. For instance, when using the 0 V to 2.5 V input range, these conditions could eventually occur on the input INA when the input buffer's (U1) supplies are different from AVDD. In such case, an input buffer with a short circuit current limitation can be used to protect the part. This analog input structure allows the sampling of the differential signal between the output of the resistive scaler and INGND. Unlike other converters, the INGND input is sampled at the same time as the inputs. By using this differential input, small signals common to both inputs are rejected as shown in Figure 10, which represents the typical CMRR over frequency. For instance, by using INGND to sense a remote signal ground, differences of ground potentials between the sensor and the local ADC ground are eliminated. During the acquisition phase for ac signals, the ADC behaves like a one-pole RC filter consisting of the equivalent resistance of the resistive scaler R/2 in series with R1 and CS. The resistor R1 is typically 100 W and is a lumped component made up of some serial resistor and the on resistance of the switches.
Except when using the 0 V to 2.5 V analog input voltage range, the ADC has to be driven by a very low impedance source to avoid gain errors. That can be done by using the driver amplifier. When using the 0 V to 2.5 V analog input voltage range, the input impedance of the ADC is very high so the ADC can be driven directly by a low impedance source without gain error. That allows putting an external one-pole RC filter between the output of the amplifier output and the ADC analog inputs to even further improve the noise filtering done by the ADC analog input circuit. However, the source impedance has to be kept low because it affects the ac performances, especially the total harmonic distortion (THD). The maximum source impedance depends on the amount of total THD that can be tolerated. The THD degradation is a function of the source impedance and the maximum input frequency, as shown in Figure 11.
-70
R = 100 -80
THD - dB
R = 50 -90
R = 11 -100
-110 0 100 FREQUENCY - kHz 1000
Figure 11. THD vs. Analog Input Frequency and Input Resistance (0 V to 2.5 V Only)
REV. A
-29-
AD15700
Driver Amplifier Choice
Although the ADC is easy to drive, the driver amplifier needs to meet at least the following requirements: The driver amplifier and the ADC analog input circuit must be able, together, to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the ADC. The noise coming from the driver is first scaled down by the resistive scaler according to the analog input voltage range used, and is then filtered by the ADC analog input circuit one-pole, low-pass filter made by (R/2 + R1) and CS. The SNR degradation due to the amplifier is:
Care should also be taken with the reference temperature coefficient of the voltage reference, which directly affects the full-scale accuracy if this parameter matters. For instance, a 15 ppm/C tempco of the reference changes the full scale by 1 LSB/C.
Scaler Reference Input (Bipolar Input Ranges)
When using the ADC with bipolar input ranges, a buffer amplifier is required to isolate the REFIN pin from the signal dependent current in the AIN pin. A high speed op amp can be used with a single 5 V power supply without degrading the performance of the ADC. The buffer must have good settling characteristics and provide low total noise within the input bandwidth of the ADC.
Power Supply
SNRLOSS
E A A 28 = log A 2 A E 2.5 N eN p A 784 + f -3 dB A A 2 E FSR E
The ADC uses three sets of power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.7 V and 5.25 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply. The ADC is independent of power supply sequencing and thus free from supply voltage induced latchup. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 12.
75
where: f-3 dB is the -3 dB input bandwidth in MHz of the ADC (9.6 MHz) or the cutoff frequency of the input filter if any is used (0 V to 2.5 V range).
PSRR - dB
70 65 60 55 50 45 40 35 1 10 100 FREQUENCY - kHz 1000 10000
N is the noise factor of the amplifier (1 if in buffer configuration). eN is the equivalent input noise voltage of the op amp in nV//Hz. FSR is the full-scale span (i.e., 5 V for 2.5 V range). For instance, when using the 0 V to 5 V range, a driver like the AD15700's internal op amp, with an equivalent input noise of 15 nV//Hz and configured as a buffer, followed by a 3.2 MHz RC filter, the SNR degrades by about 1.3 dB. The driver needs to have a THD performance suitable to that of the ADC. Figure 11 gives the THD versus frequency that the driver should preferably exceed.
Voltage Reference Input
Figure 12. PSRR vs. Frequency
POWER DISSIPATION
The ADC uses an external 2.5 V voltage reference. The voltage reference input REF of the ADC has a dynamic input impedance. Therefore, it should be driven by a low impedance source with an efficient decoupling between REF and REFGND inputs. This decoupling depends on the choice of the voltage reference, but usually consists of a low ESR tantalum capacitor connected to the REF and REFGND inputs with minimum parasitic inductance. 47 mF is an appropriate value for the tantalum capacitor when used with one of the recommended reference voltages: The low noise, low temperature drift ADR421 or AD780 voltage references The low power ADR291 voltage reference The low cost AD1582 voltage reference
In impulse mode, the ADC automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low, which allows a significant power savings when the conversion rate is reduced, as shown in Figure 13. This feature makes the ADC ideal for very low power battery applications. This does not take into account the power, if any, dissipated by the input resistive scaler, which depends on the input voltage range used and the analog input voltage even in power-down mode. There is no power dissipated when the 0 V to 2.5 V is used or when both the analog input voltage is 0 V and a unipolar range, 0 V to 5 V or 0 V to 10 V, is used. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (i.e., DVDD and DGND) and OVDD should not exceed DVDD by more than 0.3 V.
-30-
REV. A
AD15700
100000
WARP/NORMAL
10000
POWER DISSIPATION - mW
For applications where the SNR is critical, CNVST signal should have a very low jitter. One way to achieve that is to use a dedicated oscillator for CNVST generation, or at least to clock it with a high frequency low jitter clock.
t9
1000
RESET
100
10
BUSY
IMPULSE
1
0.1 1 10 100 1000 10000 SAMPLING RATE - SPS 100000 1000000
DATA
Figure 13. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
CNVST
t8
Figure 14 shows the detailed timing diagrams of the conversion process. The ADC is controlled by the signal CNVST, which initiates conversion. Once initiated, it cannot be restarted or aborted, even by the power-down input PD, until the conversion is complete. The CNVST signal operates independently of CS_ADC and RD signals.
t2 t1
CNVST
Figure 15. RESET Timing
DIGITAL INTERFACE
The ADC has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The ADC digital interface also accommodates both 3 V or 5 V logic by simply connecting the OVDD supply pin of the ADC to the host system interface digital supply. Finally, by using the OB/2C input pin, both straight binary or twos complement coding can be used. The two signals, CS_ADC and RD, control the interface. When at least one of these signals is high, the interface outputs are in high impedance. Usually, CS_ADC allows the selection of each ADC in multicircuit applications and is held low in a single ADC design. RD is generally used to enable the conversion result on the data bus.
BUSY
t4 t3 t5
MODE ACQUIRE CONVERT
t6
ACQUIRE CONVERT
t7
t8
CS_ADC = RD = 0
Figure 14. Basic Conversion Timing
t1
CNVST
In impulse mode, conversions can be automatically initiated. If CNVST is held low when BUSY is low, the ADC controls the acquisition phase and then automatically initiates a new conversion. By keeping CNVST low, the ADC keeps the conversion process running by itself. It should be noted that the analog input has to be settled when BUSY goes low. Also, at power-up, CNVST should be brought low once to initiate the conversion process. In this mode, the ADC could sometimes run slightly faster than the guaranteed limits in the impulse mode of 666 kSPS. This feature does not exist in warp or normal modes. Although CNVST is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot and undershoot or ringing. It is a good thing to shield the CNVST trace with ground and also to add a low value serial resistor (i.e., 50 W) termination close to the output of the component that drives this line.
t10
BUSY
t4 t3 t11
PREVIOUS CONVERSION DATA NEW DATA
DATA BUS
Figure 16. Master Parallel Data Timing for Reading (Continuous Read)
REV. A
-31-
AD15700
PARALLEL INTERFACE
The ADC is configured to use the parallel interface when the SER/PAR is held low. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, respectively, in Figures 18 and 19. When the data is read during the conversion, however, it is recommended that it be read only during the first half of the conversion phase. That avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry.
CSZ_ADC
CS_ADC
RD
BYTE
PINS D[15.8]
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
t12
PINS D[7.0] HI-Z
LOW BYTE
t12
HIGH BYTE
t13
HI-Z
Figure 19. 8-Bit Parallel Interface
RD
SERIAL INTERFACE
BUSY
The ADC is configured to use the serial interface when the SER/PAR is held high. The ADC outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edge of the data clock.
CURRENT CONVERSION
DATA BUS
MASTER SERIAL INTERFACE Internal Clock
t12
t13
Figure 17. Slave Parallel Data Timing for Reading (Read after Convert)
CS_ADC = 0 CNVST, RD
t1
The ADC is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held low. It also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted if desired. Depending on RDC/SDIN input, the data can be read after each conversion or during conversion. Figures 20 and 21 show the detailed timing diagrams of these two modes. Usually, because the ADC is used with a fast throughput, the mode master read during conversion is the most recommended serial mode when it can be used.
BUSY
t4 t3
In read during conversion mode, the serial clock and data toggle at appropriate instants, which minimizes potential feedthrough between digital activity and the critical conversion decisions. In read after conversion mode, it should be noted that unlike in other modes, the signal BUSY returns low after the 16 data bits are pulsed out and not at the end of the conversion phase, which results in a longer BUSY width.
SLAVE SERIAL INTERFACE External Clock
DATA BUS
PREVIOUS CONVERSION
t12
t13
Figure 18. Slave Parallel Data Timing for Reading (Read during Convert)
The BYTESWAP pin allows a glueless interface to an 8-bit bus. As shown in Figure 19, the LSB byte is output on D[7:0] and the MSB is output on D[15:8] when BYTESWAP is low. When BYTESWAP is high, the LSB and MSB are swapped and the LSB is output on D[15:8] and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 16 data bits can be read in two bytes on either D[15:8] or D[7:0].
The ADC is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS_ADC and the data are output when both CS_ADC and RD are low. Thus, depending on CS_ADC, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or discontinuous clock. A discontinuous clock can be either normally high or normally low when inactive. Figure 22 and Figure 24 show the detailed timing diagrams of these methods.
-32-
REV. A
AD15700
CS_ADC, RD EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0
t3
CNVST
BUSY
t28 t29 t30 t25 t14 t20 t18 t19 t21
1 2 3 14 15
SYNC
t24
16
t26
SCLK
t15 t27
SDOUT X D15 D14 D2 D1 D0
t16
t22
t23
Figure 20. Master Serial Data Timing for Reading (Read after Convert)
EXT/INT = 0 CS_ADC, RD
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
CNVST
t1
t3
BUSY
t17
SYNC
t25 t19 t21
2 3 14 15
t14 t20
SCLK
t24
16
t15 t18
t26
1
t27
D15 D14 D2 D1 D0
SDOUT
X
t16
t22
t23
Figure 21. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
EXT/INT = 1 CS_ADC, RD
INVSCLK = 0
RD = 0
BUSY
t35 t36 t37
SCLK 1 2 3 14 15 16 17 18
t31
SDOUT X D15
t32
D14 D13 D1 D0 X15 X14
t16
SDIN
t34
X15 X14 X13 X1 X0 Y15 Y14
t33
Figure 22. Slave Serial Data Timing for Reading (Read after Convert)
REV. A
-33-
AD15700
While the ADC is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase because the ADC provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that is toggling only when BUSY is low or, more importantly, that it does not transition during the latter half of BUSY high.
External Discontinuous Clock Data Read after Conversion
BUSY OUT BUSY BUSY
AD15700
NO. 2 (UPSTREAM) RDC/SDIN SDOUT CNVST CS_ADC SCLK
AD15700
NO. 1 (DOWNSTREAM) RDC/SDIN SDOUT CNVST CS_ADC SCLK DATA OUT
Though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. Figure 22 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning low, the result of this conversion can be read while both CS_ADC and RD are low. The data is shifted out, MSB first, with 16 clock pulses and is valid on both the rising and falling edge of the clock. Among the advantages of this method is that the conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. Another advantage is to be able to read the data at any speed up to 40 MHz, which accommodates both slow digital host interface and the fastest serial reading. Finally, in this mode only, the ADC provides a daisy-chain feature using the RDC/SDIN input pin for cascading multiple converters together. This feature is useful for reducing component count and wiring connections when desired as, for instance, in isolated multiconverter applications. An example of the concatenation of two devices is shown in Figure 23. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the opposite edge of SCLK of the one used to shift out the data on SDOUT. Therefore, the MSB of the "upstream" converter just follows the LSB of the "downstream" converter on the next SCLK cycle.
SCLK IN CS_ADC IN CNVST IN
Figure 23. Two AD15700s in a Daisy-Chain Configuration
External Clock Data Read during Conversion
Figure 24 shows the detailed timing diagrams of this method. During a conversion, while both CS_ADC and RD are low, the result of the previous conversion can be read. The data is shifted out, MSB first, with 16 clock pulses and is valid on both the rising and falling edge of the clock. The 16 bits have to be read before the current conversion is complete. If that is not done, RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. There is no daisy-chain feature in this mode and RDC/SDIN input should always be tied either high or low. To reduce performance degradation due to digital activity, a fast discontinuous clock of at least 25 MHz when impulse mode is used, and 32 MHz when normal or 40 MHz when warp mode is used, is recommended to ensure that all the bits are read during the first half of the conversion phase. It is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated. That allows the use of a slower clock speed like 18 MHz in impulse mode, 21 MHz in normal mode, and 26 MHz in warp mode.
EXT/INT = 1 CS_ADC
INVSCLK = 0
RD = 0
CNVST
BUSY
t3
t35 t36 t37
1 2 3 14 15 16
SCLK
t31
SDOUT X D15
t32
D14 D13 D1 D0
t16
Figure 24. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
-34-
REV. A
AD15700
MICROPROCESSOR INTERFACING
DVDD
The ADC is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. The ADC is designed to interface either with a parallel 8-bit or 16-bit wide interface or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the ADC to prevent digital noise from coupling into the ADC. The following sections illustrate the use of the ADC with an SPI equipped microcontroller, the ADSP-21065L and ADSP-218x signal processors.
SPI Interface (MC68HC11)
AD15700*
SER/PAR RDC/SDIN RD EXT/INT CS_ADC INVSYNC INVSCLK SYNC SDOUT SCLK CNVST
ADSP-21065L* SHARC(R)
RFS DR RCLK FLAG OR TFS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 26. Interfacing to the ADSP-21065L Using the Serial Master Mode
APPLICATION HINTS Layout
Figure 25 shows an interface diagram between the ADC and an SPI equipped microcontroller like the MC68HC11. To accommodate the slower speed of the microcontroller, the ADC acts as a slave device and data must be read after conversion. This mode also allows the daisy-chain feature. The convert command could be initiated in response to an internal timer interrupt. The reading of output data, one byte at a time, if necessary, could be initiated in response to the end-of-conversion signal (BUSY going low) using an interrupt line of the microcontroller. The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1, and SPI Interrupt Enable (SPIE) = 1 by writing to the SPI Control Register (SPCR). The IRQ is configured for edge-sensitive-only operation (IRQE = 1 in OPTION register).
DVDD
The AD15700's ADC has very good immunity to noise on the power supplies as can be seen in Figure 12. However, care should still be taken with regard to grounding layout. The printed circuit board that houses the AD15700 should be designed so the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. Digital and analog ground planes should be joined in only one place, preferably underneath the AD15700, or at least as close as possible to the AD15700. If the AD15700 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the AD15700. It is recommended to avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the switching signals like CNVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right angles to each other. This will reduce the effect of feedthrough through the board. The power supply lines to the AD15700 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supply impedance presented to the AD15700 and reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each power supply pin, AVDD, DVDD, and OVDD, close to and ideally right up against these pins and their corresponding ground pins. Additionally, low ESR 10 nF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. The DVDD supply of the AD15700 can be either a separate supply or come from the analog supply, AVDD, or from the digital interface supply, OVDD. When the system digital supply is noisy, or fast switching digital signals are present, it is recommended if no separate supply is available to connect the DVDD digital supply to the analog supply AVDD through an RC filter, and connect the system supply to the interface digital supply OVDD and the remaining digital circuitry. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes.
AD15700*
SER/PAR EXT/INT CS_ADC RD BUSY SDOUT SCLK INVSCLK CNVST IRQ
MC68HC11*
MSO/SDI SCK I/O PORT
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. Interfacing the AD15700 to SPI Interface
ADSP-21065L in Master Serial Interface
As shown in Figure 26, AD15700s can be interfaced to the ADSP-21065L using the serial interface in master mode without any glue logic required. This mode combines the advantages of reducing the wire connections and the ability to read the data during or after conversion at maximum speed transfer (DIVSCLK[0:1] both low). The ADC is configured for the internal clock mode (EXT/INT low) and acts, therefore, as the master device. The convert command can be generated by either an external low jitter oscillator or, as shown, by a FLAG output of the ADSP-21065L or by a frame output TFS of one serial port of the ADSP-21065L, which can be used like a timer. The serial port on the ADSP-21065L is configured for external clock (IRFS = 0), rising edge active (CKRE = 1), external late framed sync signals (IRFS = 0, LAFS = 1, RFSR = 1), and active high (LRFS = 0). The serial port of the ADSP-21065L is configured by writing to its receive control register (SRCTL)--see the ADSP-2106x SHARC User's Manual. Because the serial port within the ADSP-21065L will be seeing a discontinuous clock, an initial word reading has to be done after the ADSP-21065L has been reset to ensure that the serial port is properly synchronized to this clock during each following data read operation. REV. A
-35-
AD15700
The AD15700's ADC has five different ground pins: INGND, REFGND, AGND, DGND, and OGND. INGND is used to sense the analog input signal. REFGND senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. AGND is the ground to which most internal ADC analog signals are referenced. This ground must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground. The layout of the decoupling of the reference voltage is important. The decoupling capacitor should be close to the ADC and connected with short and large traces to minimize parasitic inductances.
VREF = 2.5V VDD = 5V TA = 25 C
100 90
VREF = 2.5V VDD = 5V TA = 25 C
VOUT (1V/DIV)
VOUT (50mV/DIV) GAIN = -216
10 0%
0.5 s/DIV
Figure 30. Small Signal Settling Time
DAC Circuit Information
100 90
CLOCK (5V/DIV)
VOUT = (50mV/DIV)
10 0%
The DAC is a single 14-bit, serial input voltage output. It operates from a single supply ranging from 2.7 V to 5 V and consumes typically 300 mA with a supply of 5 V. Data is written to the devices in a 14-bit word format, via a 3- or 4-wire serial interface. To ensure a known power-up state, the parts were designed with a power-on reset function. In unipolar mode, the output is reset to 0 V.
Digital-to-Analog Section
2 s/DIV
Figure 27. Digital Feedthrough
100 90
VREF = 2.5V VDD = 5V TA = 25 C CS (5V/DIV)
The DAC architecture consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 31. The four MSBs of the 14-bit data-word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of 15 matched resistors to either AGND or VREF. The remaining 10 bits of the data-word drive switches S0 to S9 of a 10-bit voltage mode R-2R ladder network.
R R VOUT 2R 2R 2R 2R 2R 2R 2R
S0
S1
S9
E1
E2
E15
VOUT (0.1V/DIV)
10 0%
10-BIT R-2R LADDER
2 s/DIV
FOUR MSBS DECODED INTO 15 EQUAL SEGMENTS
Figure 31. DAC Architecture Figure 28. Digital-to-Analog Glitch Impulse
2 s/DIV
100 90
10pF 50pF 200pF 100pF VREF = 2.5V VDD = 5V TA = 25 C
CS (5V/DIV)
With this type of DAC configuration, the output impedance is independent of code, while the input impedance seen by the reference is heavily code dependent. The output voltage is dependent on the reference voltage as shown in the following equation. VOUT = VREF D 2N
10 0%
where D is the decimal data-word loaded to the DAC register and N is the resolution of the DAC. For a reference of 2.5 V, the equation simplifies to the following.
VOUT (0.5V/DIV)
VOUT =
2.5 D 16 , 384
Figure 29. Large Signal Settling Time
giving a VOUT of 1.25 V with midscale loaded, and 2.5 V with full scale loaded to the DAC. The LSB size is VREF/16,384. -36- REV. A
AD15700
Serial Interface Output Amplifier Selection
The DAC is controlled by a versatile 3-wire serial interface that operates at clock rates up to 25 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. The timing diagram can be seen in Figure 3. Input data is framed by the chip select input, CS_DAC. After a high to low transition on CS_DAC, data is shifted synchronously and latched into the input register on the rising edge of the serial clock, SCLK. Data is loaded MSB first in 14-bit words. After 14 data bits have been loaded into the serial input register, a low to high transition on CS_DAC transfers the contents of the shift register to the DAC. Data can only be loaded to the part while CS_DAC is low.
Unipolar Output Operation
In a single-supply application, selection of a suitable op amp may be more difficult as the output swing of the amplifier does not usually include the negative rail, in this case AGND. This can result in some degradation of the specified performance unless the application does not use codes near zero. The selected op amp needs to have very low offset voltage (the DAC LSB is 152 mV with a 2.5 V reference) to eliminate the need for output offset trims. Input bias current should also be very low as the bias current multiplied by the DAC output impedance (approximately 6 kW) will add to the zero code error. Rail-to-rail input and output performance is required. For fast settling, the slew rate of the op amp should not impede the settling time of the DAC. Output impedance of the DAC is constant and code independent, but in order to minimize gain errors, the input impedance of the output amplifier should be as high as possible. The amplifier should also have a 3 dB bandwidth of 1 MHz or greater. The amplifier adds another time constant to the system, thus increasing the settling time of the output. A higher 3 dB amplifier bandwidth results in a faster effective settling time of the combined DAC and amplifier.
Force Sense Buffer Amplifier Selection
The DAC is capable of driving unbuffered loads of 60 kW. Unbuffered operation results in low supply current, typically 300 mA, and a low offset error. The DAC provides a unipolar output swing ranging from 0 V to VREF. Figure 32 shows a typical unipolar output voltage circuit. The code table for this mode of operation is shown in Table IV.
5V 2.5V 10 F
0.1 F
0.1 F
SERIAL INTERFACE
VDD CS DIN SCLK
VREF
These amplifiers can be single-supply or dual-supply, low noise amplifiers. A low output impedance at high frequencies is preferred to be able to handle dynamic currents of up to 20 mA.
OUT OP AMP UNIPOLAR OUTPUT
DAC
Reference and Ground
DGND
AGND
Figure 32. Unipolar Output
Table IV. Unipolar Code Table
As the input impedance is code dependent, the reference pin should be driven from a low impedance source. The DAC operates with a voltage reference ranging from 2 V to VDD. Although DAC's full-scale output voltage is determined by the reference, references below 2 V will result in reduced accuracy. Table IV outlines the analog output voltage for particular digital codes.
Power-On Reset
DAC Latch Contents MSB LSB 11 1111 1111 1111 10 0000 0000 0000 00 0000 0000 0001 00 0000 0000 0000 Analog Output VREF X (16383/16384) VREF X (8192/16384) = 1/2 VREF VREF X (1/16384) 0V
Assuming a perfect reference, the worst-case output voltage may be calculated from the following equation. VOUT -UNI = where: VOUT -UNI = Unipolar Mode Worst-Case Output D = Decimal Code Loaded to DAC VREF = Reference Voltage Applied to Part VGE = Gain Error in Volts VZSE = Zero Scale Error in Volts INL = Integral Nonlinearity in Volts D (VREF + VGE ) + VZSE + INL 214
The DAC has a power-on reset function to ensure the output is at a known state upon power-up. On power-up, the DAC register contains all zeros, until data is loaded from the serial register. However, the serial register is not cleared on power-up, so its contents are undefined. When loading data initially to the DAC, 14 bits or more should be loaded to prevent erroneous data appearing on the output. If more than 14 bits are loaded, only the last 14 are kept, and if fewer than 14 are loaded, bits will remain from the previous word. If the DAC needs to be interfaced with data shorter than 14 bits, the data should be padded with zeros at the LSBs.
Power Supply and Reference Bypassing
For accurate high resolution performance, it is recommended that the reference and supply pins be bypassed with a 10 nF tantalum capacitor in parallel with a 0.1 nF ceramic capacitor.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the DAC is via a serial bus that uses standard protocol compatible with DSP processors and microcontrollers. The communications channel requires a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The DAC requires a 14-bit data-word with data valid on the rising edge of SCLK. The DAC update may be done automatically when all the data is clocked in.
REV. A
-37-
AD15700
ADSP-2101/ADSP-2103 to DAC Interface
Figure 33 shows a serial interface between the DAC and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set to operate in the SPORT (Serial Port) Transmit Alternate Framing Mode. The ADSP-2101/ADSP-2103 is programmed through the SPORT Control Register and should be configured as follows: internal clock operation, active low framing, 16-bit word length. The first two bits are DON'T CARE as the DAC will keep the last 14 bits. Transmission is initiated by writing a word to the Tx Register after the SPORT has been enabled. Because of the edge-triggered difference, an inverter is required at the SCLKs between the DSP and the DAC.
TFS ADSP-2101/ ADSP-2103* DT SCLK CS_DAC DIN SCLK DAC
P3.3 80C51/ 80L51* RxD TxD
CS_DAC DIN SCLK DAC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 36. 80C51/80L51 to DAC Interface
The 80C51/80L51 provides the LSB first, while the DAC expects the MSB of the 14-bit word first. Care should be taken to ensure the transmit routine takes this into account. Usually it can be done through software by shifting out and accumulating the bits in the correct order before inputting to the DAC. Also, 80C51 outputs 2-byte word/16-bit data. Thus the first two bits, after rearrangement, should be DON'T CARE as they will be dropped from the DAC's 14-bit word. When data is to be transmitted to the DAC, P3.3 is taken low. Data on RxD is valid on the falling edge of TxD, so the clock must be inverted as the DAC clocks data into the input shift register on the rising edge of the serial clock. The 80C51/80L51 transmits its data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. As the DAC requires a 14-bit word, P3.3 (or any one of the other programmable bits) is the CS_DAC input signal to the DAC, so P3.3 should be brought low at the beginning of the 16-bit write cycle 2 8-bit words and held low until the 16-bit 2 8 cycle is completed. After that, P3.3 is brought high again and the new data loads to the DAC. Again, the first two bits, after rearranging, should be DON'T CARE.
APPLICATIONS Optocoupler Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 33. ADSP-2101/ADSP-2103 to DAC Interface
68HC11/68L11 to DAC Interface
Figure 34 shows a serial interface between the DAC and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the DAC, while the MOSI output drives the serial data lines SDIN. CS signal is driven from one of the port lines. The 68HC11/68L11 is configured for master mode; MSTR = 1, CPOL = 0, and CPHA = 0. Data appearing on the MOSI output is valid on the rising edge of SCK.
PC6 68HC11/ 68L11* PC7 MOSI SCK CS_DAC DIN SCLK DAC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 34. 68HC11/68L11 to DAC Interface
MICROWIRE to DAC Interface
The digital inputs of the DAC are Schmitt-triggered, so they can accept slow transitions on the digital input lines. This makes these parts ideal for industrial applications where it may be necessary for the DAC to be isolated from the controller via optocouplers. Figure 37 illustrates such an interface.
5V REGULATOR POWER
Figure 35 shows an interface between the DAC and any MICROWIRE compatible device. Serial data is shifted out on the falling edge of the serial clock and into the DAC on the rising edge of the serial clock. No glue logic is required as the DAC clocks data into the input shift register on the rising edge.
CS_DAC MICROWIRE* SO DIN SCLK DAC
10nF
0.1nF
VDD 10k SCLK SCLK VDD
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
VDD 10k CS CS_DAC
DAC
Figure 35. MICROWIRE to DAC Interface
80C51/80L51 to DAC Interface
VOUT
A serial interface between the DAC and the 80C51/80L51 microcontroller is shown in Figure 36. TxD of the microcontroller drives the SCLK of the DAC, while RxD drives the serial data line of the DAC. P3.3 is a bit programmable pin on the serial port that is used to drive CS_DAC.
VDD 10k DIN DIN GND
Figure 37. DAC in an Optocoupler Interface
-38-
REV. A
AD15700
Decoding Multiple DACs AMPLIFIER THEORY OF OPERATION
The CS_DAC pin of the DAC can be used to select one of a number of DACs. All devices receive the same serial clock and serial data, but only one device will receive the CS_DAC signal at any one time. The DAC addressed will be determined by the decoder. There will be some digital feedthrough from the digital input lines. Using a burst clock will minimize the effects of digital feedthrough on the analog signal channels. Figure 38 shows a typical circuit.
DAC SCLK CS_DAC DIN VDD DIN SCLK VOUT
The amplifiers are single and dual versions of high speed, low power voltage feedback amplifiers featuring an innovative architecture that maximizes the dynamic range capability on the inputs and outputs. Linear input common-mode range exceeds either supply voltage by 200 mV, and the amplifiers show no phase reversal up to 500 mV beyond supply. The output swings to within 20 mV of either supply when driving a light load; 300 mV when driving up to 5 mA. The amplifier provides an impressive 80 MHz bandwidth when used as a follower and 30 V/ms slew rate at only 800 mA supply current. Careful design allows the amplifier to operate with a supply voltage as low as 2.7 V.
Input Stage Operation
ENABLE CODED ADDRESS
EN DECODER
DAC CS_DAC DIN SCLK DGND DAC CS_DAC DIN SCLK VOUT VOUT
A simplified schematic of the input stage appears in Figure 39. For common-mode voltages up to 1.1 V within the positive supply, (0 V to 3.9 V on a single 5 V supply) tail current I2 flows through the PNP differential pair, Q13 and Q17. Q5 is cut off; no bias current is routed to the parallel NPN differential pair Q2 and Q3. As the common-mode voltage is driven within 1.1 V of the positive supply, Q5 turns on and routes the tail current away from the PNP pair and to the NPN pair. During this transition region, the amplifier's input current will change magnitude and direction. Reusing the same tail current ensures that the input stage has the same transconductance (which determines the amplifier's gain and bandwidth) in both regions of operation. Switching to the NPN pair as the common-mode voltage is driven beyond 1 V within the positive supply allows the amplifier to provide useful operation for signals at either end of the supply voltage range and eliminates the possibility of phase reversal for input signals up to 500 mV beyond either power supply. Offset voltage will also change to reflect the offset of the input pair in control. The transition region is small, on the order of 180 mV. These sudden changes in the dc parameters of the input stage can produce glitches that will adversely affect distortion.
VCC
DAC CS_DAC DIN SCLK VOUT
Figure 38. Addressing Multiple DACs
Q9 1.1V R5 50k Q5 VIP VIN
?
R6 850 Q13
I2 90mA
R1 2k
?
1 Q6
I3 25mA
R2 2k
Q3 R7 850 Q17 R8 850
Q2 R9 850 4 Q8
Q10
1 Q7 4 OUTPUT STAGE, COMMON-MODE FEEDBACK 4
?
4 Q14 1 Q15
I4 25mA Q11 1
Q16
?
I1 5mA
VEE
Q18
Q4
R3 2k
R4 2k
Figure 39. Simplified Schematic of Input Stage
REV. A
-39-
AD15700
Overdriving the Input Stage
Sustained input differential voltages greater than 3.4 V should be avoided as the input transistors may be damaged. Input clamp diodes are recommended if the possibility of this condition exists. The voltages at the collectors of the input pairs are set to 200 mV from the power supply rails. This allows the amplifier to remain in linear operation for input voltages up to 500 mV beyond the supply voltages. Driving the input common-mode voltage beyond that point will forward bias the collector junction of the input transistor, resulting in phase reversal. Sustaining this condition for any length of time should be avoided as it is easy to exceed the maximum allowed input differential voltage when the amplifier is in phase reversal.
Output Stage, Open-Loop Gain, and Distortion Versus Clearance from Power Supply
Used as a unity gain follower, the amplifier output will exhibit more distortion in the peak output voltage region around VCC -0.7 V. This unusual distortion characteristic is caused by the input stage architecture and is discussed in detail in the section covering Input Stage Operation.
Output Overdrive Recovery
Output overdrive of an amplifier occurs when the amplifier attempts to drive the output voltage to a level outside its normal range. After the overdrive condition is removed, the amplifier must recover to normal operation in a reasonable amount of time. As shown in Figure 41, the amplifier recovers within 100 ns from negative overdrive and within 80 ns from positive overdrive.
RF = RG = 2k
RG RF
VOUT IN RLT
The amplifier features a rail-to-rail output stage. The output transistors operate as common emitter amplifiers, providing the output drive current as well as a large portion of the amplifier's open-loop gain.
I1 25mA Q42 Q51 I2 25mA Q47 DIFFERENTIAL DRIVE FROM INPUT STAGE Q20 Q21 Q43 Q48 Q37 Q38 Q68 R29 300 Q27 C5 1.5pF C9 1.5pF
50V
VS = 2.5V VIN = 2.5V RL = 1k TO GND 1V 100ns
Figure 41. Overdrive Recovery
VOUT
Driving Capacitive Loads
Q49 I4 25mA Q50 I5 25mA Q44
Capacitive loads interact with an amplifier's output impedance to create an extra delay in the feedback path. This reduces circuit stability and can cause unwanted ringing and oscillation. A given value of capacitance causes much less ringing when the amplifier is used with a higher noise gain. The capacitive load drive of the amplifier can be increased by adding a low valued resistor in series with the capacitive load. Introducing a series resistor tends to isolate the capacitive load from the feedback loop, thereby diminishing its influence. Figure 42 shows the effect of a series resistor on capacitive drive for varying voltage gains. As the closed-loop gain is increased, the larger phase margin allows for larger capacitive loads with less overshoot. Adding a series resistor at lower closed-loop gains accomplishes the same effect. For large capacitive loads, the frequency response of the amplifier will be dominated by the roll-off of the series resistor and capacitive load.
1000 VS = 5 200mV STEP WITH 30% OVERSHOOT
CAPACITIVE LOAD - pF
Figure 40. Output Stage Simplified Schematic
The output voltage limit depends on how much current the output transistors are required to source or sink. For applications with very low drive requirements (a unity gain follower driving another amplifier input, for instance), the amplifier typically swings within 20 mV of either voltage supply. As the required current load increases, the saturation output voltage will increase linearly as ILOAD RC, where ILOAD is the required load current and RC is the output transistor collector resistance. For the amplifier, the collector resistances for both output transistors are typically 25 W. As the current load exceeds the rated output current of 15 mA, the amount of base drive current required to drive the output transistor into saturation will reach its limit, and the amplifier's output swing will rapidly decrease. The open-loop gain of the amplifier decreases approximately linearly with load resistance and also depends on the output voltage. Open-loop gain stays constant to within 250 mV of the positive power supply, 150 mV of the negative power supply and then decreases as the output transistors are driven further into saturation. The distortion performance of the amplifiers differs from conventional amplifiers. Typically an amplifier's distortion performance degrades as the output voltage amplitude increases.
u RS = 5
RS = 0 100
RS = 20V RS = 20 10
RG RF RS VOUT
RS = 0 , 5
CL
1 0 1 2 3 4 5 CLOSED-LOOP GAIN - V/V
-40-
Figure 42. Capacitive Load Drive vs. Closed-Loop Gain REV. A
AD15700
High Performance Single-Supply Line Driver
Even though the amplifier swings close to both rails, the amplifier has optimum distortion performance when the signal has a commonmode level halfway between the supplies and when there is about 500 mV of headroom to each rail. If low distortion is required in single-supply applications for signals that swing close to ground, an emitter follower circuit can be used at the amplifier output.
5V 10 F
0.1 F
VIN 49.9 2N3904
Figure 43 shows the amplifier configured as a single-supply gain-of-two line driver. With the output driving a back terminated 50 W line, the overall gain from VIN to VOUT is unity. In addition to minimizing reflections, the 50 W back termination resistor protects the transistor from damage if the cable is short circuited. The emitter follower, which is inside the feedback loop, ensures that the output voltage from the amplifier stays about 700 mV above ground. Using this circuit, very low distortion is attainable even when the output signal swings to within 50 mV of ground. The circuit was tested at 500 kHz and 2 MHz. Figures 44 and 45 show the output signal swing and frequency spectrum at 500 kHz. At this frequency, the output signal (at VOUT), which has a peak-to-peak swing of 1.95 V (50 mV to 2 V), has a THD of -68 dB (SFDR = -77 dB). Figures 46 and 47 show the output signal swing and frequency spectrum at 2 MHz. As expected, there is some degradation in signal quality at the higher frequency. When the output signal has a peak-to-peak swing of 1.45 V (swinging from 50 mV to 1.5 V), the THD is -55 dB (SFDR = -60 dB). This circuit could also be used to drive the analog input of a single-supply high speed ADC whose input voltage range is referenced to ground (e.g., 0 V to 2 V or 0 V to 4 V). In this case, a back termination resistor is not necessary (assuming a short physical distance from transistor to ADC), so the emitter of the external transistor would be connected directly to the ADC input. The available output voltage swing of the circuit would, therefore, be doubled.
2.49
2.49
49.9 200 49.9
VOUT
Figure 43. Low Distortion Line Driver for SingleSupply Ground Referenced Signals
1.5V
100 90 100 90
2V
10 0%
10 0%
50mV 0.5V 1s 50mV 0.2V 200ns
Figure 44. Output Signal Swing of Low Distortion Line Driver at 500 kHz
+9dBm
Figure 46. Output Signal Swing of Low Distortion Line Driver at 2 MHz
+7dBm
VERTICAL SCALE - 10dB/DIV
START 0Hz
STOP 5MHz
VERTICAL SCALE - 10dB/DIV
START 0Hz
STOP 20MHz
Figure 45. THD of Low Distortion Line Driver at 500 kHz
Figure 47. THD of Low Distortion Line Driver at 2 MHz
REV. A
-41-
AD15700
AD15700 PINOUT (TOP VIEW)
1 2 3 AGND DAC 4 5 6 7 8 9 10 11 12
A
COMMON
VREF
COMMON
COMMON
VOUT
RPAD1
RB1
-IN1
COMMON
+VS1
COMMON
A
B
CS_DAC
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
RA1
-VS1
-VS1
VOUT1
B
C
COMMON
COMMON
AGND DAC
AGND DAC
COMMON
VDD DAC
COMMON
COMMON
+IN1
COMMON
COMMON
COMMON
C
D
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
RC1
COMMON
COMMON
RESET
D
E
SCLK
DIN
DGND DAC
COMMON
COMMON
COMMON
CNVST
COMMON
COMMON
RD
D15
D14
E
F
COMMON
COMMON
+VS2
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
D13
D12
F
G
-IN2
COMMON
-VS2
COMMON
REF
COMMON
COMMON
COMMON
TEST1
BUSY
D11 RDERROR
D10 SYNC
G
H
COMMON
COMMON
-VS2
COMMON
REFGND
COMMON
COMMON
TEST0
AGND ADC
DGND ADC
D9 SCLK
D8 SDOUT
H
J
+IN2
COMMON
COMMON
COMMON
INA
COMMON
INGND
AGND ADC
AGND ADC
OGND
OVDD
DVDD
J
K
COMMON
COMMON
COMMON
VOUT2
INB
COMMON
COMMON
COMMON
PD
CS_ADC
D6 INVSCLK
D7 RDC/SDN
K
L
RC2
COMMON
COMMON
RA2
INC
COMMON
BYTE SWAP
OB/2C
IMPULSE
D1
D3 DIVSCLK1
D5 INVSYNC
L
M
COMMON
COMMON
RPAD2
RB2
IND
AVDD
WARP
SER/PAR
D0
D2 DIVSCLK0
D4 EXT/INT 11
AGND ADC
M
1
2
3
4
5
6
7
8
9
10
12
-42-
REV. A
AD15700
OUTLINE DIMENSIONS 144-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-144)
Dimensions shown in millimeters
A1 CORNER INDEX AREA
12 11 10 9 8 7 6 5 4 3 2 1
10.00 BSC SQ
A1
TOP VIEW
A B C D E F G H J K L M
1.70 MAX
DETAIL A
0.80 BSC 8.80 BSC
DETAIL A
0.85 MIN
0.25 MIN
0.55 SEATING 0.50 PLANE 0.45 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-205AC NOTES 1. THE ACTUAL POSITION OF THE BALL POPULATION IS WITHIN 0.15 OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES 2. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.08 OF ITS IDEAL POSITION RELATIVE TO THE BALL POPULATION
0.12 MAX COPLANARITY
REV. A
-43-
AD15700 Revision History
Location 2/03--Data Sheet changed from REV. 0 to REV. A. Page
Edit to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edit to ADC PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Edit to Figure 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
C03025-0-2/03(A) PRINTED IN U.S.A.
Edits to AMPLIFIER ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
-44-
REV. A

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